US10142368Cache-coherency protocol for multi-core processorsUSTier S
US10218547Low-power tensor accelerator datapathUSTier S
US10311902Speculative out-of-order execution engineUSTier S
US10398715Unified virtual memory across CPU and GPUUSTier S
US10472330Hardware root-of-trust for secure bootUSTier S
US10561284Speculative branch-prediction pipelineUSTier A
US10612938Memory-bandwidth compression for GPUsUSTier A
US10689451Mixed-precision matrix-multiply acceleratorUSTier A
US10744120Coherent multi-die interconnect fabricUSTier A
US10812677Adaptive voltage-frequency scaling controllerUSTier A
US10897203Network-on-chip router with virtual channelsUSTier A
US10923948Out-of-order instruction scheduling unitUSTier B
US11008372Hardware page-table walker with prefetchUSTier B
US11087655Vector load-store coalescing engineUSTier B
US11154019Last-level cache replacement policy engineUSTier B
US11231204Hardware prefetcher with stride detectionUSTier B
US11302588DMA engine with scatter-gather descriptorsUSTier B
US11388471SIMD lane-masking for predicated executionUSTier B
US11455120Reorder buffer with early register reclaimUSTier B
US11522934On-chip interconnect for accelerator clustersUSTier B
US11603847Coherent cache partitioning for QoSUSTier C
US11689210Thermal-aware core migration schedulerUSTier C
US11744655Instruction-cache way predictionUSTier C
US11812039Store-to-load forwarding predictorUSTier C
US11889472Adaptive thermal throttling for multi-core SoCsUSTier C
US11954118Configurable interrupt-routing matrixUSTier C
US12012677Power-gated register file for low-leakage coresUSTier D
US12087451Debug-trace buffer with timestampingUSTier D
US12154930Performance-counter sampling unitUSTier D
US12231044Boundary-scan test access portUSTier D